NCP1605DR2G【PDF 25/32 页】IC PFC CONTROLLER CCM/DCM 16SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录45

21页 22页 23页 24页 [25页]26页 27页 28页 29页

NCP1605, NCP1605A, NCP1605B

http://onsemi.com

Figure 64. Standby Management

300 mV

95.5% of the Regulation Level

Drive

OUT

SKIP

OUT

Pin1

CONTROL

Remark:

" Skip cycle is not allowed during the PFC startup phase

to avoid that it interferes with the softstart. That is why,

skip cycle is enabled only when pfcOK is high.

" Each working phase of the burst mode starts smoothly as

Pin 3 is grounded at the beginning of it. This softstart

capability is effective to avoid the audible noise that

could possibly result from such a burst operation.

" The circuit leaves the standby mode when the output

voltage goes below 95.5% of its regulation level and

Pin1

is above 330 mV (300 mV + 30 mV hysteresis).

Oscillator / Synchronization Section

The oscillator generates the clock signal to set the PWM

latch and turn the MOSFET on. The oscillator frequency is

set by the capacitor that is applied to Pin 8. Typically,

820 pF force about 60 kHz. The maximum allowable

oscillator frequency is 250 kHz. The clock frequency can

also be driven by an external synchronization signal.

This block contains two main parts (refer to Figure 66):

" The arrangement that consists of charging/discharging

current sources, a switch and a comparator. When used

in oscillator mode, a capacitor is connected between

Pin 8 and ground. A current source (100 mA) charges the

Pin 8 capacitor until its voltage exceeds VoscH. At that

moment, the comparator (COMP_OSC) turns high and

activates the discharge current source (200 mA). As a

consequence, Pin 8 actually sinks 100 mA that discharge

the oscillator capacitor to VoscL. At that moment, the

comparator turns low and initiates a new charge phase. If

the circuit is to be externally triggered, the

synchronization signal must cross VoscL and VoscH to

properly turn on and off the COMP_OSC comparator.

Also the synchronization signal must be low impedance

enough not to be distorted by the Pin 8 source and sink

currents.

" The storing circuitry that contains a latch and some

gates. The raising edge of the COMP_OSC output sets

the CLOCK Generation latch to turn high the CLK

signal. If the timing capacitor of Pin 7 is properly

discharged (V

Pin4

<50 mV leading to C

OK high), the

PWM block is ready for a new cycle and CLK can

force the signal V

SET

in high state. As a consequence,

the PWM latch sets. In addition, V

SET

resets the

CLOCK Generation latch to make it ready for the next

oscillator cycle. The two inverters of Figure 66, simply

generate some delay to ensure that V

SET

keeps high

long enough to set the PWM latch and reset the

CLOCK Generation latch (longer delay than that

produced by the two gates, may actually be necessary).

The oscillator / Synchronization block is designed to set the

switching frequency.

However, the coil current can possibly be non zero at the

end of a clock period and the circuit would enter Continuous

Conduction Mode (CCM) if the MOSFET turned on in that

moment. In order to prevent CCM, the storing circuitry of

the oscillator / synchronization block, memorizes the

COMP_OSC rising edge (thanks to the CLOCK

Generation latch) and delays the next MOSFET conduction

time until the coil current has totally vanished (that is until the

signal DT is high DT is generated by the current sense

block so that it is high during the deadtime and low

otherwise). In other words, CRM operation is obtained (refer

to Figure 65).

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式